Error Correction in an Electronic Circuit

ABSTRACT

An electronic circuit has a data producing circuit ( 12 ), such as a matrix of memory cells. A capture circuit ( 14 ) has e an input coupled to the data producing circuit ( 10 ) for capturing the data signals after allowing a selected part of the data producing circuit to drive the input of the capture circuit. An error detection circuit ( 15 ) detects errors in the captured data signals. In response to detection of an error in particular data signals, the error detection circuit causes recapture of the particular data signals, allowing the data producing circuit ( 10 ) to drive the data signals at the input of the capture circuit ( 14 ) during a second time interval until recapture, the second time interval having a longer duration than the first time interval. This makes it possible to select the duration of the first time interval allowing for average driving speed of circuit parts (e.g. memory cells), without using a duration designed to account for worst case driving speed that may occur due to spread. Errors caused by spread are corrected by rereading with an increased time interval for driving the input of the capture circuit. Preferably, the duration of the first time interval is regulated so that on average a predetermined error rate occurs.

The invention relates to a digital electronic circuit and in particularto an electronic circuit that comprises one or more memory matrices.

Prevention of errors is becoming an increasingly important design aspectof integrated circuits. U.S. Pat. No. 6,360,346, for example, discloseshow an error correcting code (ECC) can be used to correct errors duringmemory read operations. This type of correction makes use of the factthat most bits will typically be read correctly from a memory, only afraction of the bits producing errors. If there are too many errorsmemory blocks, or even the whole circuit is discarded.

There are many potential sources of errors in integrated circuits. Inthe past the large number of memory cells in a memory, and the need toreduce the size of cells to the limit of what is technologicallypossible have made it difficult to produce error free memories with highyield. With the progressive reduction of semi-conductor feature sizestatistical spread in the number of implanted atoms in differenttransistors is becoming a new source of errors. Typically this type oferror does not lead to completely defective memory cells, but rather itmakes it impossible to find a single threshold that suits all cells. USpatent application No. 2002/0122344 discloses a circuit which reducesthe effect of this spread. Nevertheless errors are difficult to preventand it has been found to be more efficient to accept a number ofdefective cells, using correction techniques to correct errors.

Speed is another important performance requirement of electroniccircuits. The higher the speed the more computations can be executed persecond, making the electronic circuit more valuable. The maximumpossible speed of electronic circuits is limited by the time needed toallow signals to develop in the circuit. Digital signals are representedby analog signals such as voltages and or currents that can only changeat a finite rate, making it necessary to leave some time for the signalsto develop before the represented digital values can be captured.

A memory provides an illustration of this requirement. A memory matrixtypically contains word lines for addressing the cells and bit lines androws and columns of memory cells. Each word line corresponds to a rowand the cells in each row are coupled to a respective bit line. Each bitline corresponds to a column, cells in each column being coupled incommon to a respective bit line. Capture circuits, which typicallyinclude a sense amplifier, are coupled to the bit lines. When a cell isaccessed, a signal on the word line of its row makes the cell influencea signal on the bit line of its column. After a delay that allows thisinfluence to develop into a detectable signal, the capture circuit istriggered to latch into a state determined by the signal. Since manycells are coupled to the same bit line the influence of the cell on thesignal on the bit line is relatively weak, which makes it necessary touse a relatively long delay. This limits the speed of the memorycircuit.

The need to give signals sufficient time to develop before they can becaptured sets a ceiling on the maximum possible speed. If the signal iscaptured to soon unpredictable outputs result not just for individualbits, but for entire words, which makes it impossible to use errorcorrection techniques. Accordingly, much work has been invested inminimizing the required time, for example by using smaller circuitdimensions, which reduces capacitances that counteract signaldevelopment, by reducing the required signal swing or by using strongerdrive circuits.

Nevertheless it is unavoidable that the speed must be limited.Conventionally this is done by setting the clock speed of the integratedcircuit, or at least of the memory, to a value that allows sufficientsignal development before the start of capture. It is also known to setthe speed adaptively, in response to the output signal developmentcaused by a reference cell with known content. In the prior art thiskind of technique is used as a time reference for a memory as a whole,or at least for groups of memory cells to ensure sufficient time forsignal development. In this case the memory is self-timed.

In this way a worst-case scenario determines the speed. If there is astatistical spread in the speed of different memory cells, some cellswill develop signals more slowly than others, but it is impossible topredict which cells. Therefore, the reference cell approach will predictless accurately the timing of the other memory cells. To avoid anoverdose of errors the speed must be set a number of standard deviationsof the speed below the speed that is acceptable for average cells. Thelarger the memory, the lower the speed must be set.

Among others, it is an object of the invention to provide for anelectronic circuit that is capable of performing with a low error ratewith an average speed that is higher than the speed dictated byworst-case design for that error rate.

Among others, it is an object of the invention to reduce the effect ofstatistical spread in the number of implanted ions on the maximumaverage operating speed of an integrated circuit.

A circuit according to one aspect of the invention is set forth in Claim1. The circuit produces data signals and captures the data signals,capture starting after a first time interval during which the dataproducing circuit (such as addressed memory cells) are allowed to drivethe input of the capture circuit (capture, as used herein, means causingthe digital output of the capture circuit to become fixed so that it isno longer influenced by subsequent development of its input signals).According to the invention production and capture is retried with alonger second time interval when an error is detected, or at least whenan uncorrectable error is detected. In a memory, in particular, anaddressed cell is may be addressed again when an (uncorrectable) erroris detected, and data from the cell is captured the second time intervalafter addressing, or the capture circuit is reset and allowed to bedriven during the second time interval after release from reset.

Recapture of data with extended duration represents a loss of throughputspeed, but it makes it possible to use a shorter duration for firstcapture, because errors due to excessive speed at first reading can betolerated. As a result the average throughput rate, the number ofcorrect data signals that can be produced per second, is higher than canbe achieved by setting the first time interval to allow for worst caseconditions. This is particularly advantageous for circuits with largenumbers of sub-circuits, such as memory cells, that have a statisticalspread in the maximum possible capture speed. In this case the higheraverage speed is effectively used to compensate excessively low speed ofsome sub-circuits.

In an embodiment the duration of the first time interval, used tocapture data signals first when no error has yet been detected in thedata signal, is regulated so that a set error rate occurs. Thus, thespeed of the circuit can be optimized. In a further embodiment theduration is regulated to a set (non zero) rate of uncorrectable errorsand/or recapture with extended duration is used in response to detectionof uncorrectable errors. This can even be used by itself, withoutrecapture with extended duration, for example if a certain amount oferrors can be tolerated. In a circuit with a plurality of memories thatcan be used in parallel, the distribution of data over the memories canbe adapted to the different average speeds that can be realized by thedifferent memories. A larger fraction of the data may be stored inmemories with a higher speed and a smaller fraction of the data may bestored in memories with a lower speed. In this way the average speed canbe optimized.

Recaptured data takes the place of the originally erroneous data duringfurther processing of the data, at least if no error correction waspossible. This may be realized for example by recapturing the data withextended duration between capture of data for subsequent addresses withnormal duration, and insertion of the recaptured data at its originalposition for further processing, out of order with the data for thesubsequent addresses. As an alternative, block based reading may beused, data from a block that contained errors being recaptured afterreading of the block has been completed.

These and other objects and advantage of the invention will be describedin more detail using the following figures.

FIG. 1 shows an electronic circuit

FIG. 2 illustrates a trade-off between read delay and average throughput

FIG. 1 shows an electronic circuit, comprising a data producing circuitin the form of a memory matrix 12, an addressing circuit 10, a sensingcircuit 14, an error correction and detection circuit 15, a timingcircuit 16, a buffer memory 17 and a processing circuit 18. Addressingcircuit 10 has an addressing output coupled to memory matrix 12. Memorymatrix 12 has bit line outputs coupled to sensing circuit 14. Sensingcircuit 14 has digital outputs coupled to error correction and detectioncircuit 15. Error correction and detection circuit 15 has a firstcontrol output coupled to timing circuit 16, a second control outputcoupled to addressing circuit 10 and a data output coupled to buffermemory 17. Timing circuit 16 has timing control outputs coupled toaddressing circuit 10 and sensing circuit 14. Buffer memory 17 has anoutput coupled to processing circuit 18.

In operation addressing circuit 10 successively addresses wordscorresponding to groups of memory cells in memory matrix 12. Whenaddressed, the cells from a group are coupled to the bit lines so thatthey influence the signal levels on the bit lines. Sensing circuit 14captures data from the bit lines, converting the signals on the bitlines into digital values. Error correction and detection circuit 15receives the digital values and detects and corrects errors in thesedigital values. For this purpose error correction and detection circuit15 typically makes use of an Error Correcting Code (ECC), which definesa set of multi-bit codewords selected so that the codewords mutuallydiffer at least at a predetermined number of bits. Data stored in eachgroup of cells memory matrix 12 represents a word selected from the setof codewords, so that in the absence of errors the digital value outputto error correction and detection circuit 15 corresponds to the selectedcodeword from the set of codewords. But due to errors the digital valuemay differ from the selected codeword. Error correction and detectioncircuit 15 detects this, and determines which codeword differs leastfrom the digital value. This codeword corresponds to a decoded datavalue, which error correction and detection circuit 15 writes to buffermemory 17. Processing circuit 18 reads and processes the decoded datavalues from buffer memory 17.

Although addressing circuit 10 is shown as a separate circuit for thesake of clarity, it should be understood that in practice the addressesmay be selected by processing circuit 18, making processing circuit 18in a sense part of addressing circuit 10.

Timing circuit 16 controls timing of reading. Timing circuit 16 providesstart signals to addressing circuit 10, which control the timing ofaddressing of groups of memory cells in memory matrix 12. Timing circuit16 also provides capture signals to sensing circuit 14. The capturesignals control when signals from the bit lines will be used to capturedata. The way in which the capture signals are applied depends on thetype of sense amplifier. For example, one type of sense amplifier (suchas used in DRAMs for example) contains a pair of cross-coupled inverterswhich are enabled by the capture signal, one inverter having an inputcoupled to the bit line, the other having an input coupled to areference line (not shown). When enabled, such a sense amplifier drivesitself to one of two stable states, dependent on the initial signal onthe bit line. In this case the capture triggers enabling of theinverters. Another type of sensing circuit contains a latch with aninput coupled to a bit line (typically via an amplifier or acomparator). In this case the latch is clocked in response to thecapture signal. Other types of sensing circuits that use capture timingsignals are also possible. In each case the sensing circuit captures adigital value determined by a signal or signals on the bit lines at atime determined by the capture signal.

One additional advantage of the proposed method is that power is savedsince the bit-lines are driven for a shorter time on average. Therefore,the voltage swing is lower, resulting in less power dissipation. Thesense-amplifiers and meta-stable latches also consume power. Whencontrolling the timing, the sense amplifier and latches are preferablyenabled with a delay, to avoid keeping them in a meta-stable state for alonger period of time.

The duration of the delay between the start signal and the capturesignal at least partly determines the cycle frequency of the memory.Timing circuit 16 typically applies a new start signal to addressingcircuit 10 with a predetermined time interval after generating thecapture signal for capturing the previous data value. Hence, the longerthe duration of the delay between the start signal and the capturesignal, the longer the cycle time between successive start signals.

Timing circuit 16 sets the duration of the delay between the startsignal and the capture signal so that in a majority of cases the signalson the bit lines get sufficient time to develop to a level that enablescapture occurs with sufficient accuracy that no errors, or at least withso few errors that error correction is possible. However, the delay isnot set to a duration so that all cells get sufficient time to developsignals that are sufficiently large to enable reliable detection.Statistical spread in the number of implanted atoms in transistors ofthe cells may have the effect that the drive strength of some of thecells is too weak to allow capture with sufficient reliability after thedelay determined by timing circuit 16.

In a first embodiment error correction and detection circuit 15 signalsdetection of an uncorrectable error in a particular data value toaddressing circuit 10 and timing circuit 16. In response, addressingcircuit 10 readdresses the group of memory cells that gave rise to thisparticular data value. Timing circuit 16 controls the delay between thestart of readdressing of this group of cells and capture by sensingcircuit 14. Timing circuit 16 sets this delay for rereading to a highervalue than used for addressing and sensing of signal values cells duringfirst reading. Error correction and detection circuit 15 receives thedata value read with the increased delay and writes it into buffermemory 17 at, the place of the data value for the original readoperation. As an alternative, if the address of the erroneous data valuestill controls the selected group of memory cells, readdressing may beomitted and rereading may proceed immediately, after resetting sensingcircuit with increased delay after resetting. (In a known sensingcircuit for example, resetting includes decoupling the connectionbetween the bit lines and the sensing circuit and equalizing the inputsignals, of the sensing circuit. After reset, equalizing is discontinuedand the bit lines are coupled-to the input of the sensing circuit again,to start a new sensing operation).

Optionally, the data value read with the extended delay is also used towrite back to the memory cells from which it was read. If the error wascaused by overly short timing this provides no additional advantage, butif other sources of error exist, which cannot be distinguished fromtiming errors, write back may reduce the probability of recurrence ofthese errors.

Typically processing circuit 18 processes data values in packets ofmultiple words. Processing circuit 18 starts processing of a packet isstarted once all data for the packet has been read successfully in thisway. Alternatively, buffer memory 17 may be a breathing buffer, like aFIFO buffer that absorbs variations in delay before valid data isavailable. In this case it may be necessary to pause reading from memorymatrix if a low error rate occurs, when the FIFO buffer signals that itis full. In another embodiment processing circuit performs a functionlike image decoding wherein frames need to be produced beforepredetermined time points, but variations in the delay before deliveryof data are permissible before these time points. In this case that taskperformed by processing circuit 18 may be designed so that it nominallyleaves some spare time before the time points, if no read errors occur,processing circuit 18 remaining in step with reading (i.e. pausing if areread is required).

It should be appreciated this embodiment relies on a trade-off:decreasing the delay between the start signal and the capture signalincreases the number of memory cycles that can be performed per second.But if the delay is decreased this increases the number of additional(longer) cycles that is needed to read corrected data, thereby reducingthe number of data values that can be read per second.

FIG. 2 illustrates this trade-off. Three curves are shown as a functionof the normal cycle-time T used for reading from memory matrix 12. Afirst curve 20 shows the number of cycles needed for rereading due toerrors. As can be understood, for a high cycle time T little or noerrors occur, because even the weakest memory cells get sufficient timeto develop signals that are large enough to be captured reliably. As aresult the number of cycles for rereading is small. As the cycle timedecreases an increasing number of memory cells has insufficient drivestrength, until for zero cycle time all memory cells have insufficientdrive strength. As a result the number of cycles for rereading increaseswith decreasing cycle time T.

A second curve 22 (a straight line) shows the normal cycle time neededto read data if no error occurs. A third curve 24 shows the averagecycle time obtained by the longer cycle time for rereading, multipliedby the fraction of memory cells that requires rereading, added to thenormal cycle time. As can be seen, an optimum cycle time occurs(indicated by arrow 28). This optimal cycle time should be contrastedwith a “safe” worst case cycle time (indicated by arrow 26) selected toavoid an excessive number of errors. As can be appreciated, by usingrereading the average cycle time, and thereby the throughput time ofpackets time can be reduced.

Various possibilities exist for selecting the higher delay duringrereading. For example, a predetermined worst-case higher delay may beused during rereading, which will ensure correct reading with a requiredminimum probability. As another example, a first higher delay durationmay be used first and if this again results in an error the data may bereread again, using a second, even higher delay. The second delay may bea predetermined worst case delay or it may be followed by rereading at athird even higher delay and so on.

In a further embodiment error correction and detection circuit 15triggers rereading immediately when an error is detected. If the circuitis sufficiently fast to detect the error before the start of the nextread operation this may be used to ensure that no next address is readbefore the preceding address has been read successfully. However, inanother embodiment rereading may be done out of order, inserting areread of a word after a predetermined number of successive addresseshas been read subsequently to first reading of the word. In yet anotherembodiment rereading may be performed after a predetermined block ofaddresses has been read. In this embodiment addressing circuit 10 forexample records the addresses for which rereading is required, setstiming circuit 16 to the higher delay after completion of reading fromthe block, and next addresses memory matrix 12 at the addresses forwhich a need to reread has been recorded.

In a second embodiment timing circuit 16 uses the error rate of errorssignalled by error correction and detection circuit 15 to regulate thedelay between the start signal and the capture signal. If the averageerror rate is below a set level timing circuit 16 reduces the delay. Ifthe average error rate is above a set level timing circuit 16 increasesthe delay. Various methods of selecting the set level are possible,generally designed to select the set level so that maximum throughput isrealized with no more than an acceptable number of errors. In oneembodiment a maximum tolerable error rate R is specified dependent onthe function of the apparatus (in a television set, for example, thisrate follows from a rate at which frame errors may occur). Giveninformation about the ECC that is used it is determined which bit errorrate B in the uncorrected words leads to errors that cannot be correctedwith the ECC at an uncorrectable error rate R corresponding to themaximum tolerable error rate (typically if n−1 errors can be correctedR=B^(n)). Next the speed is regulated so that the observed average biterror rate assumes a value slightly below the computed bit error ratedB.

Any type of regulation may be used. The rate of errors may be averagedfor example and a difference between the average and the set value maybe used to adjust the delay. As an alternative, the delay may beincreased by a first step for each word wherein an error is detected anddecreased by a second step for each word wherein no error is detected,the ratio between the first and second step being selected dependent onthe set level. In a further embodiment the step size may be adapteddependent on a detected number of errors in a word.

This second embodiment may be combined with the first embodiment toselect the delay between the start signal and the capture signal forfirst reading, so as to optimize the average compound throughput speed(curve 24 in FIG. 2). The set value of the error rate may be selectedfrom an analysis of the statistical spread for example. Otherwise timingcircuit may be arranged to measure the throughput for different valuesof the delay and to set the delay at the value that realizes the highestaverage throughput.

However, the second embodiment can also be used separately from thefirst embodiment, for example if the performance specification of thecircuit permits a certain average error rate (e.g. as noise during audioor video signal decoding). In another embodiment the data from memorymay contain additional error correction information that permitsprocessing circuit 18 to correct errors up to a certain average rate. Inthis case the speed may be regulated so that this error rate isrealized.

Although a particular embodiment of the invention has been disclosed, itwill be appreciated that the invention is not limited to thisembodiment. For example, although an application to reading from amemory matrix 12 has been shown, the invention may be applied to othercircuits as well. For example, the invention may be applied to errorscaused by capturing data at the output of a logic circuit too quickly.In this case errors at the output of the logic circuit may be detectedby using circuits to generate redundant signal, or by performing someconsistency check on the output signal. In one embodiment, the delaybetween the application of input data to the logic circuit and captureof results is adapted in a control loop so that the error rate isregulated to a set level. In another embodiment, the circuit responds todetection of an error by applying the same input data anew at the inputof the logic circuit and repeating capture, this time with a largerdelay. In this way, a high average throughput can be realized, whilecorrecting errors if slow parts of the logic circuits are involved.Reapplication of the same input data can be realized for example byrestarting a sub-task executed by the circuit, e.g. by processing thesame data for a second time. Of course both these embodiment may be usedin combination.

As another example of alternative applications of the invention, aplurality of memory matrices may be provided in parallel, so that datacan be reread from any individual memory matrix independently ofrereading from the other memory matrices. A common processing circuit isprovided that processes combined data from the parallel memories. Inthis embodiment the circuit may be arranged to control the distributionof the combined data over the memories dependent on the throughput ratethat can be realized with each memory. Preferably the data isdistributed so that the fastest memories are filled completely and theslowest memories are left empty, or used for processing tasks that donot require a high throughput speed. As an alternative respectivefractions of the combined data are stored in respective memories, thefraction stored in a memory being proportional the average throughputrate of the memory divided by the sum of the average throughput rates ofall memories (the average throughput rate being the average number ofwords that can be produced from the memory per second).

Furthermore it should be realized that in some embodiments the wordsstored in memory matrix 12 need not be words from an ECC. For example,the information to detect and/or correct errors in the words may besupplied from another source than memory matrix 12. Nor is it necessarythat error detection and correction should be performed a word at atime. For example, errors may be detected and corrected in a block ofwords that have been read successively from memory matrix 12. In thiscase rereading of erroneous words may be delayed until the whole blockhas been read and analysed for errors. Similarly, regulation of thedelay between start signals and capture signals may be performed on ablock basis.

Furthermore it should be appreciated that error detection and correctioncircuit 15 may be realized as a dedicated circuit, but that its functionmay also be performed by processing circuit 18. In both cases dedicatederror correction hardware and/or suitably programmed programmablehardware could be used. If processing circuit 18 performs errordetection, it may request rereading with a longer delay at any time andat its own discretion, omitting a reread if no corrected data is neededfor processing purposes, for example.

In a further embodiment, when an error that can be corrected only byreading with increased delay is detected for a group of memory cells, itis recorded in an auxiliary memory that for that group of cells anincreased delay is needed. In this case, during a next reading of thegroup of cells, the auxiliary memory is consulted and if it is recordedthere that an increased delay is needed, the increased delay is usedimmediately, without first attempting to read with the shorter delay.The information from the auxiliary memory may also be used forincreasing the delay for the same selected groups of cells duringwriting. This reduces write errors, since delay related errors forspecific groups of cells typically occur both for reading and writing.

1. An electronic circuit comprising a data producing circuit having anoutput for producing data signals; a capture circuit having an inputcoupled to the output of the data producing circuit for capturing thedata signals; a timing circuit for controlling a duration of a firsttime interval during which the data producing circuit is allowed todrive the data signals at the input of the capture circuit untilcapture; an error detection circuit having an input coupled to thecapture circuit, for detecting errors in the captured data signals, theerror detection circuit being coupled to the timing circuit for, inresponse to detection of an error in particular data signals, causingrecapture of the particular data signals, allowing the data producingcircuit to drive the data signals at the input of the capture circuitduring a second time interval until recapture, the second time intervalhaving a longer duration than the first time interval.
 2. An electroniccircuit according to claim 1, wherein the data producing circuitcomprises a memory matrix and an addressing circuit that generatesaddressing signals for selecting memory cells in the memory matrix thedata signals being driven from the addressed memory cells, dependent onthe content of the addressed memory cells.
 3. An electronic circuitaccording to claim 2, wherein said first and second time interval lastfrom application of the addressing signals to the memory matrix untilsubsequent capture and recapture respectively.
 4. An electronic circuitaccording to claim 1, wherein said first and second time interval lastfrom release of the capture circuit from a reset state until subsequentcapture and recapture respectively.
 5. An electronic circuit accordingto claim 1, wherein the timing circuit is arranged to regulate, undercontrol of an average rate of detected errors, the duration of thefirst-time interval for capturing data signals subsequent to the errors.6. An electronic circuit according to claim 1, wherein the data signalsrepresent codewords from an Error Correcting Code, the error detectioncircuit being arranged to correct errors according to the ErrorCorrecting Code, the error detection circuit causing recapture inresponse to detection of an error that does not meet a criterion forcorrectability for the Error Correcting Code, but not in response toerrors that meet said criterion.
 7. An electronic circuit according toclaim 2, wherein the addressing circuit is arranged to read data for ablock of successive addresses, to store information that identifies oneor more reread addresses for which the error detection circuit hasdetected errors during reading from addresses of the block, and toreread data from addressed determined by the stored reread addresseswith the second time interval after completion of a first cycle ofreading from addresses from the block.
 8. An electronic circuitaccording to claim 2, wherein the addressing circuit is arranged togenerate addressing signals for a first address followed in a temporalsequence by further addresses for reading using said first timeinterval, and to insert, in response to detection of an error in thedata signal for the first address, the first address among the furtheraddresses at a predetermined number of positions after the first addressin the temporal circuit, for rereading from the first address using thesecond time interval.
 9. An electronic circuit according to claim 1,wherein the error detection circuit is coupled to the addressingcircuit, which is arranged to extend a duration during which anaddressing signal is applied to the memory matrix in response todetection of an error in the data signals read using that addressingsignal, the timing circuit causing the capture circuit to return to areset state and allowing the addressed memory cells to drive datasignals at the input of the capture circuit during second time intervalfrom release the reset state until subsequent recapture.
 10. Anelectronic circuit according to claim 1, wherein the first time intervalhas a value that substantially minimizes a sum as a function of theduration of the first time interval, wherein the sum is a sum of saidduration and the duration of the second time interval weighted by afraction of data signals that contain said errors when said first timeinterval is used for first capture.
 11. An electronic circuit accordingto claim 1, comprising a processing circuit and a buffer memory coupledbetween the capture circuit and the processing circuit for transfer ofinformation derived from the data signals, the buffer memory beingarranged to absorb timing variations due to rereading of data signals.12. A method of processing data, the method comprising applyingsuccessive control signals to a data producing circuit; producingsuccessive data signals with a selected part of the data producingcircuit, that are selected under control of the control signals;allowing the selected part to drive an input of a capturing circuit withthe data signals; capturing the data signals after driving during afirst time interval; detecting whether an error has occurred in thecaptured data driven by a particular selected part of the data producingcircuit; recapturing the data signals after allowing the particularselected part of the data producing circuit drive the input of thecapture circuit during a second time interval, which has a longerduration than the first time interval, in response to detection of theerror.
 13. A method according to claim 12, wherein the duration of thefirst time interval is selected so that it substantially minimizes a sumas a function of the duration of the first time interval, wherein thesum is a sum of the duration of the first time interval and the durationof the second time interval weighted by a fraction of data signals thatcontain said errors when said duration delay of the first time intervalis used for first capture.
 14. A method according to claim 12, whereindata is read from a memory matrix the selected parts of the dataproducing circuit being addressed cells in the memory matrix theaddressed cells driving the input of the capture circuit.
 15. A methodaccording to claim 12, comprising the step of regulating the duration ofthe first time interval dependent on a detected error rate.
 16. Anelectronic circuit comprising a data producing circuit, having an outputfor producing data signals from selectable parts of the data producingcircuit; a capture circuit having an input coupled to the output of thedata producing circuit for capturing the data signals; a timing circuitfor controlling a duration of a time interval during which the selectedparts are allowed to drive the input of the capture circuit untilcapture; an error detection circuit having an input coupled to thecapture circuit, for detecting errors in the captured data signals, theerror detection circuit being coupled to the timing circuit, forregulating the duration of the time interval for capturing data signalssubsequent to the errors, so that an average error rate is regulated toa set value greater than zero.
 17. A method of processing data themethod comprising generating successive control signals; producing datasignals from circuits selected in response to respective ones of thecontrol signals; capturing the data signals, after allowing the selectedcircuit to drive an input of a capture circuit during a time interval;detecting errors in the captured data signals; regulating the durationof the time interval subsequent to the errors, so that an average errorrate is regulated to a set value greater than zero.